USB v2.0 Soft PHY and Device Controller
USB2 PHY
USB 2.0 Full High Speed Solution | NXP Semiconductors
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
The Next-Generation Interconnect | Mouser
GOWIN Semiconductor - USB 2.0 PHY & Device Controller IP Certification Webinar - NEWS & EVENTS-Redtree-Solutions
USB2.0 PHY – Silicon Library Inc.
OpenFive-USB IP Subsystem-USB 3.1 Controller-USB 3.2 Retimer
USB 2.0 Device Controller for SoC Designs | Cadence IP
USB 2.0 PHY IP core | Arasan Chip Systems
USB 2.0 OTG IP Core | Arasan Chip Systems
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB 2.0 PHY Verification
TUSB1210-Q1 data sheet, product information and support | TI.com
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USB 2.0 Solutions | Arasan Chip Systems
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB 2.0 PHY for SoC Designs | Cadence IP
USB2.0 Host Transceiver PHY IP Core
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 Full High Speed Solution | NXP Semiconductors
HSIC USB 2.0 PHY IP
Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
The USB 2.0 Device IP core | Arasan Chip Systems
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
